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MC74HC244A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver
High-Performance Silicon-Gate CMOS
The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two active-low output enables. The HC244A is similar in function to the HC240A.
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20 PDIP-20 N SUFFIX CASE 738 1 1 20 20 1 SOIC-20 DW SUFFIX CASE 751D 1 HC244A AWLYYWWG MC74HC244AN AWLYYWWG
20
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 136 FETs or 34 Equivalent Gates Pb-Free Packages are Available*
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC 244A ALYWG G
20 1
20 SOEIAJ-20 F SUFFIX CASE 967 1
74HC244A AWLYWWG
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
April, 2006 - Rev. 11
Publication Order Number: MC74HC244A/D
MC74HC244A
PIN ASSIGNMENT
ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1 DATA INPUTS A4 B1 B2 B3 A2 A3 A1 2 4 6 8 11 13 15 17
LOGIC DIAGRAM
18 16 14 12 9 7 5 3 YA1 YA2 YA3 YA4 YB1 YB2 YB3 YB4 NONINVERTING OUTPUTS
FUNCTION TABLE
Inputs Enable A, Enable B A, B Outputs YA, YB L H Z
B4
L L L H H X Z = high impedance
OUTPUT ENABLES
1 ENABLE A 19 ENABLE B
PIN 20 = VCC PIN 10 = GND
ORDERING INFORMATION
Device MC74HC244AN MC74HC244ANG MC74HC244ADW MC74HC244ADWG MC74HC244ADWR2 MC74HC244ADWR2G MC74HC244ADT MC74HC244ADTG MC74HC244ADTR2 MC74HC244ADTR2G MC74HC244AF MC74HC244AFG MC74HC244AFEL MC74HC244AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 18 Units / Rail 18 Units / Rail 38 Units / Rail 38 Units / Rail 1000 Tape & Reel 1000 Tape & Reel 75 Units / Rail 75 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 40 Units / Rail 40 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC244A
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I IIIII I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIII II IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIII I I I II I I IIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIII I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIII I III II IIIIIIIIIIIIIIIIIIIIIII II II I I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I III II II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I
II I IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package Storage Temperature mW Tstg TL - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V (Figure 1) VCC = 4.5 V VCC = 6.0 V
VCC
- 55 0 0 0
+ 125 1000 500 400
_C ns
tr, tf
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| v 20 mA
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| v 20 mA
V
Vin = VIH |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VIL |Iout| v 20 mA
2.48 3.98 5.48 0.1 0.1 0.1
2.34 3.84 5.34 0.1 0.1 0.1
VOL
Maximum Low-Level Output Voltage
V
Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VCC or GND
0.26 0.26 0.26
0.33 0.33 0.33
Iin
Maximum Input Leakage Current
0.1
1.0
1.0
mA
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MC74HC244A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Guaranteed Limit v 85_C 5.0 Symbol IOZ Parameter Test Conditions VCC V 6.0 - 55 to 25_C 0.5 v 125_C 10 Unit mA Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 mA NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit v85_C 115 60 23 20
Symbol tPLH, tPHL
Parameter
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - -
- 55 to 25_C 96 50 18 15
v125_C 135 70 27 23 165 80 33 28 165 80 33 28 90 32 18 15 10 15
Unit ns
Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3)
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4)
110 60 22 19 110 60 22 19 60 23 12 10 10 15
140 70 28 24 140 70 28 24 75 27 15 13 10 15
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 3)
ns
Cin
Maximum Input Capacitance
pF pF
Cout
Maximum Three-State Output Capacitance (Output in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 34
CPD
Power Dissipation Capacitance (Per Buffer)*
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
tr 90% 50% 10% tPLH 90% 50% 10% tTLH tPHL tf VCC tPZL 50% tPZH OUTPUT Y 50% tPHZ tPLZ 10% 90% GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
DATA INPUT A OR B OUTPUT YA OR YB
VCC GND
ENABLE A OR B
50%
OUTPUT Y tTHL
Figure 1.
Figure 2.
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MC74HC244A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
PIN DESCRIPTIONS
INPUTS A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17)
function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state.
OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3)
Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROLS Enable A, Enable B (Pins 1, 19)
Device outputs. Depending upon the state of the output-enable pins, these outputs are either noninverting outputs or high-impedance outputs.
Output enables (active-low). When a low level is applied to these pins, the outputs are enabled and the devices
LOGIC DETAIL
TO THREE OTHER A OR B INVERTERS
ONE OF 8 INVERTERS DATA INPUT A OR B VCC
YA OR YB
ENABLE A OR ENABLE B
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MC74HC244A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74HC244A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
K REF
M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
20X
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
20
11
K K1
0.25 (0.010)
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC244A
PACKAGE DIMENSIONS
SOEIAJ-20 CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC244A/D

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